`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/05/07 17:11:12
// Design Name: 
// Module Name: lite_fnym
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module lite_fnym(
    input wire clk,
    input wire rst_n,
//    input ready,
    input wire [127:0] data,
    input wire valid_in,
    output reg valid_out,
    output  [127:0] data_o
);

    reg [63:0] data_r,data_r1;
    always @(posedge clk or negedge rst_n) 
        if (!rst_n)
            data_r1 <= 0;
        else
            data_r1 <= data_r;
    assign data_o = {data_r1,data_r};
    
    genvar i;
    generate
        for (i = 0; i < 64; i = i + 1) begin : GROUP
            always @(posedge clk or negedge rst_n) begin
                if (!rst_n) begin
                    data_r[i] <= 1'b0;
                end else if(valid_in) begin
                    case (data[2*i + 1 : 2*i])
                        2'b00, 2'b11: data_r[i] <= 1'b0; // 丢弃
                        2'b01: data_r[i] <= 1'b1;
                        2'b10: data_r[i] <= 1'b0;
                        default: data_r[i] <= 1'b0;
                    endcase
                end
            end
        end
    endgenerate

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            valid_out <= 1'b0;
        else
            valid_out <= valid_in;
    end
    
    
endmodule
